As shown in FIG. 1, a common computer system (100) includes a central processing unit (CPU) (102), memory (104), and numerous other elements and functionalities typical of today's computers (not shown). The computer (100) may also include input means, such as a keyboard (106) and a mouse (108), and output devices, such as a monitor (110). Those skilled in the art will understand that these input and output means may take other forms in an accessible environment. In one or more embodiments of the invention, the computer system may have multiple processors and may be configured to handle multiple tasks.
The CPU (102) is an integrated circuit (IC) and is typically one of many integrated circuits included in the computer (100). Integrated circuits may perform operations on data and transmit resulting data to other integrated circuits. The correct operation of the computer relies on accurate transmission of data between integrated circuits.
An IC operates between two power supply lines, one at a higher voltage potential and one at a lower voltage potential. In the present invention, the higher voltage potential power supply line is designated VDD. The lower voltage potential power supply line may supply any voltage potential lower than the higher voltage potential power supply line, but typically it will supply a zero voltage potential also referred to as ground. In the present invention, the lower voltage potential power supply line is designated VSS. The difference between VDD and VSS is a power supply voltage potential. The power supply maintains the power supply voltage potential.
FIG. 2 shows a diagram of an IC (252), a chip package (250), and a power distribution network for the IC (252). The power distribution network includes impedances Z1 (204), Z2 (206), and Z3 (208). Impedances (204, 206, 208) may include resistive, capacitive, and inductive elements and model both the inherent parasitics of the power distribution network and added components that may affect the voltage potentials supplied to the IC (252). The power propagated to the IC (252) must traverse from a power supply (202) across the power distribution network to the chip package (250).
Two power supply lines (292, 294) propagate power from the power distribution network to the chip package (250) on which the IC (252) is mounted. On the chip package (250), other components and parasitics, represented by impedances Z1P (254), Z2P (256), and Z3P (258), affect the voltage potentials propagated to the IC (252) and may contain resistive, capacitive, and inductive elements. The voltage potentials supplied to the IC (252) on lines (272) and (274) may vary from the voltage potentials produced by the power supply (202) due to effects of the impedances (204, 206, 208) in the power distribution network and the impedances (254, 256, 258) in the chip package (250).
The impedances (204, 206, 208) in the power distribution network and the impedances (254, 256, 258) in the chip package form a “parasitic tank circuit” that may resonate if a frequency of switching of elements within the IC (252) closely matches a resonant frequency of the parasitic tank circuit. A power supply resonance is manifested as an oscillation or “ringing” of the power supply voltage potential at the resonant frequency. Ringing of the power supply voltage potential may affect the IC (252) by limiting the power of transmitted signals. In order to avoid ringing and its undesirable effects on IC operation, the power supply resonance must be suitably controlled.
Conventional methods of controlling resonance include connecting an external capacitor between the power supply lines (292) and (294). This connection creates a local power supply that may supply power to the IC (252) as needed. However, this method does not significantly reduce the ringing caused by impedances (254, 256, 258) in the chip package (250).
FIG. 3 shows a detailed view of the IC (252) shown in FIG. 2. Like items in FIG. 2 and FIG. 3 are shown with like reference numbers. In FIG. 3, the IC (252) includes IC logic (360) and an output buffer (362). The IC (252) may operate with a data clock signal supplied on line (312). The data clock signal is used to synchronize data input to and output from the IC (252). Data output by the IC logic (360) is sent on line (364) to the output buffer (362) for transmission on line (266) to a receiver (not shown). In one or more embodiments, the IC logic (360) and the output buffer (362) may use separate power supply lines.
Inside the IC (252), the power supply voltage potential is affected further by resistive and capacitive elements on the IC (252). Power pads (368, 369) mark the interface between the IC (252) and the chip package (250 shown in FIG. 2). VDD is supplied to the power pad (368) and propagated to the output buffer (362) on line (376). VSS is supplied to the power pad (369) and propagated to the output buffer (362) on line (378). The power supply lines (376) and (378) are wires on the IC (252) and present some resistance to current flow. In FIG. 3, the resistance of line (376) is represented by resistors (380, 381). The resistance of line (378) is represented by resistors (382, 383). There is also some parasitic capacitance between the power supply lines (376, 378) and other lines (not shown) in the IC (252). In FIG. 3, capacitances between the power supply lines (376, 378) and other lines (not shown) are represented by impedances Z1 (384) and Z2 (385), respectively.